`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:37:20 03/17/2022
// Design Name:   regfile
// Module Name:   E:/OpenMIPS/test_regfile.v
// Project Name:  OpenMIPS
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: regfile
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_regfile;

	// Inputs
	reg clk;
	reg rst;
	reg we;
	reg [4:0] waddr;
	reg [31:0] wdata;
	reg re1;
	reg [4:0] raddr1;
	reg re2;
	reg [4:0] raddr2;

	// Instantiate the Unit Under Test (UUT)
	regfile uut (
		.clk(clk), 
		.rst(rst), 
		.we(we), 
		.waddr(waddr), 
		.wdata(wdata), 
		.re1(re1), 
		.raddr1(raddr1), 
		.re2(re2), 
		.raddr2(raddr2)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		we = 0;
		waddr = 0;
		wdata = 0;
		re1 = 0;
		raddr1 = 0;
		re2 = 0;
		raddr2 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

